Mixed signal processor units are integrated circuits that have contained thereon a digital processing section and analog section. The analog section is typically comprised of an analog multiplexer and an analog-to-digital converter, in addition to a digital-to-analog converter. This allows analog data to be sampled on a plurality of analog data inputs, converted to digital signals and then supplied to the processing section for processing thereof. On the digital processing side, the digital processor can operate at multiple frequencies. These frequencies are from internal clocks that generate a plurality of frequencies. Typically, there are two distinct clocks, a high frequency clock and a low frequency clock. The low frequency clock is typically utilized such that the processor can go into a low power mode wherein the processing is carried out at a very low frequency and consumes considerably less power. Typically, the high frequency rate is on the order of 20-25 MHz and the low frequency clock rate is on the order of 32 KHz. The problem is that, when operating at the low frequency, the ADC must also operate at the low frequency. Typically, the ADC is facilitated utilizing a successive approximation algorithm that requires a plurality of bits to be tested during each data conversion cycle. Thus, at the low frequency, the throughput of the ADC is very slow, since its conversion clock can not operate at higher than the clock rate of the high frequency clock. Further, both at the high frequency and the low frequency, the data conversion operation can be influenced by noise generated in the digital processing section. Therefore, if both the ADC and the digital processing section are operating on the same clock frequency, it is possible for noise to be injected into the analog section from the digital section, this being a conventional problem in mixed signal devices.